The present invention relates to a semiconductor output circuit and a bus buffer semiconductor integrated circuit, and more particularly, to a bus buffer semiconductor integrated circuit which reduces the power consumption and noise of an output circuit caused by a capacitive load.
For example, a capacitive load is connected via an external wiring line to an output terminal of an output circuit formed as a semiconductor integrated circuit. When the level of a signal at the output terminal of the output circuit is inverted, the output circuit operates to charge or discharge the capacitive load. Thus, when the external wiring line is long, the capacitive load is considered to be large, which demands the output circuit to have a high load driving capability. This is because, in the case where the load driving capability is low in spite of the fact that the capacitive load is large, much time is required to invert the signal level of the output terminal, which results in the operation of the output circuit becomes dull or slow. However, it is further considered that a parasitic inductance caused by the external wiring line is equivalently connected between the output terminal and capacitive load. For this reason, in the event where the output circuit has a high load driving capability, when the signal level of the output terminal is inverted, there may occur such a situation that undershoot, overshoot and/or ringing takes place in the signal of the output terminal under the influences of the parasitic inductance. Undershoot is such a phenomenon that when the potential at the output terminal varies from the high level to the low level, the potential at the output terminal is reduced to a level lower than the low level. Overshoot is such a phenomenon that when the potential at the output terminal varies from the low level to the high level, the potential at the output terminal is increased to a level higher than the high level. Further, ringing is such a phenomenon that after generation of undershoot or overshoot, the voltage at the output terminal vibrates.
When the undershoot, overshoot and/or ringing occurs, this may cause a circuit connected to the output terminal to be erroneously operated. Further, when ringing takes place, this causes variations of a power voltage, which may cause erroneous operation of a circuit within the same chip for receiving the power voltage. Furthermore, when ringing takes place, an electromagnetic resonance phenomenon (EMI) causes noise to generate in the peripheral space of the output circuit.
There has been suggested a prior art output circuit that can suppress generation of undershoot, overshoot and/or ringing while retaining a high load driving capability.
Disclosed in JP-A-2-250425 and JP-A-2-301098 are output circuits which includes a plurality of n-channel MOS transistors connected in parallel to an output terminal and a plurality of p-channel MOS transistors connected in parallel to the output terminal so that, when an output voltage falls, the number of the n-channel MOS transistors to be turned ON is increased in a step-like manner, while, when the output voltage rises, the number of the p-channel MOS transistors to be turned on is increased in a step-like manner.
Also disclosed in JP-A-3-41818 is an output circuit which includes a plurality of n-channel MOS transistors connected in parallel to an output terminal and a plurality of p-channel MOS transistors connected in parallel to the output terminal so that, when an output voltage falls, the number of the n-channel MOS transistors to be turned ON is decreased in a step-like manner, while, when the output voltage rises, the number of the p-channel MOS transistors to be turned ON is decreased in a step-like manner.
JP-A-61-108223 discloses an output circuit which includes an n-channel MOS transistor is designed so that, when an output voltage falls, the gate and drain of the transistor are connected to an output terminal at the initial stage of the falling of the output voltage in a diode connection between the output terminal and a grounding terminal, and then the gate is cut off from the output terminal to provide a predetermined voltage.
There is disclosed in JP-A-2-89419 an output circuit wherein, in a period from a change of an output signal from its high level to low level to a change of the output signal again to the high level, an n-channel MOS transistor is provided for injecting a current to an output terminal continuously for a period after the output signal falls to a predetermined voltage until the output signal rises again to the predetermined voltage.
Also disclosed in JP-A-2-89419 an output circuit which includes an n-channel MOS transistor for injecting a current to an output terminal, and wherein, in a period from a change of an output signal from its high level to low level to a change of the output signal again to the high level, the n-channel MOS transistor operates to inject the current to the output terminal continuously for a period after the output signal falls to a predetermined voltage until the output signal rises again to the predetermined voltage. Accordingly, it has been clarified by the inventor of the present application that even after the voltage at the output terminal is reduced to the low level to suppress the generation of undershoot, the above n-channel MOS transistor continues to inject the current to the output terminal until the voltage of the output terminal rises again to the above predetermined level, which results in that useless power not contributing to the undershoot suppression is inevitably consumed. It has also been found by the inventor that since such a circuit is provided as to supply a predetermined voltage to the gate of the n-channel MOS transistor constantly regardless of the voltage levels of the input and output signals, the power consumption of the output circuit is disadvantageously made much large.